Embodiments of the present invention relate generally to a nonvolatile memory device and a method of manufacturing the same and more particularly to improving the resistance of select lines and simplifying the manufacturing processes of nonvolatile memory devices.
A nonvolatile memory device, such as a NAND flash memory, includes a plurality of strings ST in a cell array region. The strings ST are described below in more detail with reference to FIG. 1, which is a circuit diagram showing the memory cell array of a NAND flash memory device.
Referring to FIG. 1, the memory cell array of the NAND flash memory device includes a plurality of strings ST, where each string is coupled between a common source line CSL and a drain contact DCT coupled to a bit line BL. Each of the strings ST includes a plurality of memory cells MC coupled in series between a drain select transistor DST and a source select transistor SST.
The drain select transistor DST couples the string ST to the bit line BL, and the source select transistor SST couples the string ST to the common source line CSL. The drain select transistors DST are coupled to a drain select line DSL, and the source select transistors SST are coupled to a source select line SSL. Furthermore, the memory cells MC are coupled respectively to rows of word lines WL arranged between the source select line SSL and the drain select line DSL.
In general, the gates of the transistors SST, DST and memory cells MC in a string ST in a NAND flash memory device are formed simultaneously by stacking the common layers and then patterning the stacked layers. FIG. 2 is a cross-sectional view showing a part of a string to describe formation of the gates in a string ST.
Referring to FIG. 2, the gates of memory cells MC coupled to respective word lines WL and the gate of a source select transistor SST coupled to a source select line SSL are formed by sequentially a first conductive layer 15, a dielectric layer 17, and a second conductive layer 19 over a gate insulating layer 13 formed over a semiconductor substrate 11 and then patterning them. Although not shown, the gate of a drain select transistor DST coupled to a drain select line DSL is formed using the same process as that used to form the gate of the source select transistor SST. It should be readily understood that the meaning of “on” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only mean “directly on” something but also include the meaning of “on” something with an intermediate feature or a layer therebetween and that “over” not only means the meaning of “over” something may also include the meaning it is “over” something with no intermediate feature or layer therebetween (i.e., directly on something).
In each of the gates of the memory cells MC, the first conductive layer 15 is used as a floating gate into which electrons are injected or from which electrons are discharged, and the second conductive layer 19 is used as a control gate. Accordingly, in a memory cell MC, the first conductive layer 15 and the second conductive layer 19 are electrically insulated with the dielectric layer 17 interposed therebetween.
On the other hand, in the case of a source select transistor SST and the drain select transistor DST, the first conductive layer 15 and the second conductive layer 19 must be electrically coupled, because the gates of the source select transistor SST and the drain select transistor DST do not require a floating gate structure. Accordingly, when forming a source select transistor SST or a drain select transistor DST, a contact hole H, through which the first conductive layer 15 is exposed, is formed in the dielectric layer 17 by etching a region of the dielectric layer 17 prior to the stacking of the second conductive layer 19. The source select transistor SST and the drain select transistor DST are formed in this manner to correspond with the regions in which the source select line SSL and the drain select line are to be formed. Thus, the second conductive layer 19 stacked over the dielectric layer 17 having a contact hole H formed therethrough is electrically coupled to the first conductive layer 15 through the contact hole H in the region where the source select line SSL and the drain select line are to be formed.
To form a contact hole H in the dielectric layer 19 requires an additional mask process of forming the contact hole H. One mask process requires at least 6 processes including a deposition process, a cleaning process, an etch process, and so on. Thus, an additional mask process leads to more complicated manufacturing processes, which are undesirable.
After forming the gates of a string, impurity ions are implanted into the semiconductor substrate 11 between the gates to form the junctions 11a. A spacer 21 is formed on the sidewalls of the gates, and a space between the gates is filled with a first interlayer dielectric layer 23. Next, a common source line CSL is formed and coupled to the junction 11a between the neighboring source select lines SSL. Furthermore, although not shown in FIG. 2, a drain contact plug (that is, part of a drain contact) is coupled to the junction between the drain select lines. The common source line CSL and the drain contact plug may be formed by etching the first interlayer dielectric layer 23 so that the junction 11a between the source select lines SSL and the junction between the drain select lines DSL are exposed and then filling a part from which the first interlayer dielectric layer 23 has been removed with a conductive material.
After forming the common source line CSL and the drain contact plug as described above, a plurality of auxiliary lines 29a is formed. The auxiliary lines 29a may be formed by (1) forming a second interlayer dielectric layer 27 on the first interlayer dielectric layer 23 including the common source line CSL and the drain contact plug, (2) etching the parts of the second interlayer dielectric layer 27, and (3) filling the removed parts of the second interlayer dielectric layer 27 with a metal material.
Although not shown in FIG. 2, the auxiliary lines 29a are interconnected through a contact structure provided in the strapping region of a cell array region. The auxiliary lines 29a are coupled to the common source line CSL, so as to improve the resistance of the common source line CSL and the source line bouncing phenomenon.
However, increasing the loads of the source select line SSL and the drain select line DSL are becoming more difficult in light of the ongoing effort to achieve more highly integrated and smaller sized semiconductor memory devices. When the select lines are overloaded, the time to program a NAND flash memory device inevitably increases because the time taken to supply a program voltage to a specific word line is increased. Furthermore, noise may be generated because the stability of a signal is not secured.
To improve the resistance (i.e., to reduce resistance) of the select lines, a metal silicide such as cobalt silicide (CoSi2) may be used as the second conductive layer 19. A metal silicide is chiefly formed by patterning a polysilicon layer used as the second conductive layer 19, stacking a metal layer on the patterned polysilicon layer, and then performing a silidation process using an annealing process. The width of the patterned polysilicon layer is wider in the source and drain select lines SSL, DSL than in the word lines WL.
By performing an annealing process, the amount of metal from the metal layer diffused into the patterned polysilicon layer is smaller in the source and drain select lines SSL, DSL than in the word lines WL. Consequently, the thickness of the metal silicide layer in the word lines WL is thicker than the thickness of the metal silicide layer in the source and drain select lines SSL, DSL. The metal from the metal silicide layer should not be spreading to the dielectric layer 17. Therefore, the target thickness of a metal silicide layer is based on the thickness of the rather thick metal silicide layer in the word lines WL.
For this reason, improving the resistance of the source and drain select lines SSL, DSL is difficult because the metal silicide layer having a thickness enough to improve the resistance may not be formed in the source and drain select lines.